A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
FIG. 1 depicts a cross-section of a portion 10 of a conventional semiconductor wafer that has been prepared for selective patterning of at least one semiconductor device feature. As shown, portion 10 includes a substrate 12, a feature layer 14, and a resist mask 16 that forms windows 17a-c. Substrate 12 is typically a selectively patterned and/or doped semiconductor material having one or more active regions (not shown) that are integral to the semiconductor device. By way of example, if the semiconductor device is a metal oxide semiconductor (MOS) transistor, then the substrate 12 typically includes an active source region, an active drain region, and one or more isolating regions. Feature layer 14, in this case, typically includes a tunnel oxide layer over which at least one electrically conductive layer, for example, polysilicon, is deposited and subsequently patterned to form at least one gate using conventional fabrication techniques. Resist mask 16 typically includes an organic spin-on compound that is selectively exposed to deep-UV radiation and further processed to reveal specific portions of the top surface 15 of feature layer 14 through windows 17a-c, for example.
In order to selectively pattern feature layer 14, portion 10 (i.e., the semiconductor wafer) is normally placed in an etching tool (not shown) and exposed to a plasma that contains reactive and/or ionized species of gas molecules which chemically react and/or physically bombard the exposed portions of feature layer 14. For example, FIG. 2 depicts portion 10 following exposure to a plasma 18 that has removed, or etched away, portions of feature layer 14 to create etched openings 20a, 20b and 20c through windows 17a, 17b and 17c, respectively. Etched openings 20a-c extend through feature layer 14 to reveal portions of top surface 13 of underlying substrate 12.
Resist mask 16, having served its function is then removed, or stripped away, using conventional techniques. FIG. 3 depicts portion 10 after resist mask 16 has been stripped away. As shown, a plurality of device features 14a-d have been selectively formed from feature layer 14. Device features 14a-d, for example, can be gates of MOS transistors.
Controlling the resulting size and/or shape of a device feature (e.g., 14b) is often critical to functioning of the applicable device. For example, in certain semiconductor devices it is preferred that the design feature have substantially planar and/or vertical sidewalls. Further, in certain semiconductor devices having a plurality of like device features it is preferred that each of the device features meet certain size and shape constraints.
With this in mind, there are several problems with the device features 14a, 14b, 14c, and 14d, as depicted in FIG. 3. These problems will be pointed out by referring to device features 14b and 14c. As shown, device features 14b and 14c do not have substantially vertical sidewalls, with respect to top surface 13. In particular, device feature 14b has sloping sidewalls 24a on opposing sides, and device feature 14c has a sloping sidewall 24a adjacent to device feature 14b and a sloping sidewall 24b adjacent to design feature 14d. Notice that the angle, with respect to top surface 13, of sloping sidewalls 24a is different than the angle, with respect to top surface 13, of sloping sidewalls 24b. Consequently, device feature 14b has a different shape and size than device feature 14c.
The difference in shapes of device features 14b and 14c can be traced to the etching process, and more particularly to the resist mask 16. Referring back to FIG. 2, a residue 22 tends to form when plasma 18 contacts resist mask 16 during the etching process. As shown, residue 22 can build up within the etched openings 20a-c, and on the sidewalls of the design features. Residue 22, which typically includes harder to etch polymers, tends to reduce the etching capability of plasma 18 to feature layer 14. As a result, the sidewalls of the various device features tends to be non-vertical and in certain cases non-planar, as well.
The final shape of a given sidewall depends on several factors, including the amount of residue 22 that actually forms. The amount of residue 22 that forms appears to depend, at least partially, on the window 17a-c (e.g., shape, size, width, thickness, etc.) formed by resist mask 16. For example, since window 17c is wider than windows 17a and 17b there tends to be more residue 22 build-up within etched opening 20c, which is formed through window 17c. Consequently, device features 14b and 14c are shaped differently and may perform differently.
Thus, there is a need for methods that provide increased process control during the formation of device features by reducing the deleterious effects of residue build-up.